Automatic Implementation of Secure Silicon (AISS)*
Abstract
*Previously part of Beyond Scaling - Design The Automatic Implementation of Secure Silicon (AISS) program will enable a design tool and Intellectual Property (IP) ecosystem where security is pervasive and can be naturally incorporated into chip design with minimal effort and expense. The program will enable rapid evaluation of architectural alternatives in platform integration where security is considered with conventional design economics, together being power, area, speed, and security. The program will advance multi-level provenance and integrity validation techniques for design through advances in current methods or invention of novel technical approaches and demonstrate new capabilities in the context of reduced instruction set computing (RISC) architectures or computer processors. AISS aims to automate inclusion of scalable defense mechanisms into chip designs to enable optimization of the security versus economics trade space. It will protect advanced chips from known attack strategies by incorporating security into a highly automated system aimed at reducing design time while maximizing exploration of architectural alternatives. As a result, the DoD applications will benefit from more secure chips becoming pervasive whether designed specifically for the defense systems or commercially procured.
Document Details
- Document Type
- Accomplishment
- Publication Date
- Oct 01, 2021
- Source ID
- 095221b8d7e00ac22010259b086975cd
Related Documents
- Root: ELECTRONICS TECHNOLOGY