Cortical Processor
Abstract
Capturing complex spatial and temporal structure in high-bandwidth, noisy, ambiguous data streams to meet DoD's needs cannot be achieved even by state-of-the-art signal/image analysis systems. However, there is a processing structure in nature, the mammalian neocortex, that efficiently captures spatial and temporal structure and routinely solves the most difficult recognition problems in real-time and is a general purpose structure for a range of sensor data processing and motor control execution. The Cortical Processor program will leverage simplified models of known cortical operation to develop a new processor architecture that is optimized for running a family of algorithms known as Hierarchical Temporal Memory (HTM), providing new levels of performance and capabilities to a broad range of data recognition problems. HTM models map well to simple, massively parallel, signal processor arrays, and a cortical processor leveraging advances in dense memory structures on a complementary metal-oxide semiconductor (CMOS) chip running at a few watts can perform orders of magnitude larger tasks than HTM systems simulated by commercial efforts on large data-center clusters. And with certain specialized circuits, several orders of magnitude improvement in throughput and efficiency will be possible with the cortical processor, enabling a wide range of powerful, ultra-low power, embedded applications. The Cortical Processor program includes basic scientific exploration into a variety of topics central to the development of this fundamentally new computing methodology. The ultimate goal of the Cortical Processor program is to fabricate an accelerator/coprocessor, in silicon, that contains thousands of reconfigurable, interconnected HTM modules. HTM algorithm and data representation research will be conducted to determine optimal implementation to efficiently utilize the collective operation of the individual modules to achieve the unique features and functionality required by the cortical processor. Each of the cortical processor modules will communicate with a large subset of other nodes requiring development of dense interconnect technology and research into a variety of on-chip network optimizations for the architecture to achieve the connectivity required. Opportunities for significant improvements in power efficiency and speed will be achieved by leveraging recent advances in dense memory structures, such as multi-level floating gates, processors in memory, or 3D integration. Applied research for the program is budgeted in PE 0602303E, Project IT-02.
Document Details
- Document Type
- Accomplishment
- Publication Date
- Oct 01, 2015
- Source ID
- 0d62b5c09d54d6d1cbcae47ae6713304