Orientation‐Controlled Selective‐Area Epitaxy of III–V Nanowires on (001) Silicon for Silicon Photonics

Abstract

Monolithic integration of III–V nanowires on silicon platforms has been regarded as a promising building block for many on‐chip optoelectronic, nanophotonic, and electronic applications. Although great advances have been made from fundamental material engineering to realizing functional devices, one of the remaining challenges for on‐chip applications is that the growth direction of nanowires on Si(001) substrates is difficult to control. Here, catalyst‐free selective‐area epitaxy of nanowires on (001)‐oriented silicon‐on‐insulator (SOI) substrates with the nanowires aligned to desired directions is proposed and demonstrated. This is enabled by exposing {111} planes on (001) substrates using wet chemical etching, followed by growing nanowires on the exposed planes. The formation of nanowire array‐based bottom‐up photonic crystal cavities on SOI(001) and their coupling to silicon waveguides and grating couplers, which support the feasibility for on‐chip photonic applications are demonstrated. The proposed method of integrating position‐ and orientation‐controllable nanowires on Si(001) provides a new degree of freedom in combining functional and ultracompact III–V devices with mature silicon platforms.

Document Details

Document Type
Pub Defense Publication
Publication Date
Jun 02, 2020
Source ID
10.1002/adfm.202002220

Entities

People

  • Brian C. Regan
  • Brian Zutter
  • Diana L. Huffaker
  • Hyunseok Kim
  • Ting‐yuan Chang
  • Wook‐jae Lee

Organizations

  • Air Force Office of Scientific Research
  • Cardiff University
  • Electronics and Telecommunications Research Institute
  • National Science Foundation
  • University of California
  • University of California, Los Angeles

Tags

Readers

  • Integrated Circuit Design and Technology.
  • Nanofabrication and Microfabrication.
  • Nanoscale Plasmonic Nanotechnology

Technology Areas

  • Microelectronics
  • Microelectronics - Graphene