A Monolithic Stochastic Computing Architecture for Energy Efficient Arithmetic
Abstract
As the energy and hardware investments necessary for conventional high‐precision digital computing continue to explode in the era of artificial intelligence (AI), a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since, unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting, etc., SC can implement the same using simple logic gates. While it is possible to accelerate SC using traditional silicon complementary metal–oxide–semiconductor (CMOS) technology, the need for extensive hardware investment to generate stochastic bits (s‐bits), the fundamental computing primitive for SC, makes it less attractive. Memristor and spin‐based devices offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here, the limitations of existing and emerging technologies are overcome, and a standalone SC architecture embedded in memory and based on 2D memtransistors is experimentally demonstrated. The monolithic and non‐von‐Neumann SC architecture occupies a small hardware footprint and consumes a miniscule amount of energy (<1 nJ) for both s‐bit generation and arithmetic operations, highlighting the benefits of SC.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Dec 08, 2022
- Source ID
- 10.1002/adma.202206168
Entities
People
- Harikrishnan Ravichandran
- Joan Redwing
- Nicholas Trainor
- Saptarshi Das
- Thomas F. Schranghamer
- Yikai Zheng
Organizations
- Army Research Office
- National Science Foundation
- Pennsylvania State University