A Pathway to Thin GaAs Virtual Substrate on On‐Axis Si (001) with Ultralow Threading Dislocation Density
Abstract
With recent developments in high‐speed and high‐power electronics and Si‐based photonic integration, the concept of monolithic III–V/Si integration through epitaxial methods is gaining momentum. However, the performance and reliability of epitaxially grown devices are still limited by defects in the semiconductor material, especially the threading dislocation density (TDD). Herein, a novel “asymmetric step‐graded filter” structure grown by molecular beam epitaxy (MBE) is proposed based on a systematic study of the commonly used techniques for threading dislocation reduction for high‐quality GaAs on Si (001) growth. The proposed structure greatly enhances the plastic relaxation in the filter layers. A surface TDD lower than 2 × 106 cm−2 is achieved with a total buffer thickness of only 2.55 μm. This provides a clear pathway to further reduce defect density down to the theoretical limit in the 105 cm−2 regime with a thin buffer structure.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Aug 14, 2020
- Source ID
- 10.1002/pssa.202000402
Entities
People
- Aidan A. Taylor
- Arthur C. Gossard
- Chen Shang
- Eamonn T Hughes
- Jennifer Selvidge
- John E. Bowers
- Justin C. Norman
- Kunal Mukherjee
Organizations
- Defense Advanced Research Projects Agency
- University of California, Santa Barbara