Is negative capacitance FET a steep-slope logic switch?
Abstract
The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantum-capacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 10, 2020
- Source ID
- 10.1038/s41467-019-13797-9
Entities
People
- Kaustav Banerjee
- Wei Cao
Organizations
- Army Research Office
- Core Research for Evolutional Science and Technology
- Intel Corporation