Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer
Abstract
A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ∼69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V·s, indicating a positive influence on top-gate device performance even without any backside bias.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jul 17, 2017
- Source ID
- 10.1063/1.4995242
Entities
People
- Angelica Azcatl
- Chadwin D Young
- Paul K. Hurley
- Pavel Bolshakov
- Peng Zhao
- Robert M Wallace
Organizations
- Defense Advanced Research Projects Agency
- National Science Foundation
- University College Cork
- University of Texas at Dallas