Testability Synthesis for Jumping Carry Adders
Abstract
Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 2002
- Source ID
- 10.1080/10655140290010079
Entities
People
- Chien-in Henry Chen
- Mahesh Wagh
Organizations
- LSI Corporation
- United States Air Force
- Wright State University