A Low Latency Parallel Bus Interface for High-Speed multi-FPGA RT-Simulations

Document Details

Document Type
Pub Defense Publication
Publication Date
Aug 03, 2021
Source ID
10.1109/ests49166.2021.9512344

Entities

People

  • Andrea Benigni
  • Herbert L. Ginn
  • Michele Difronzo

Organizations

  • Office of Naval Research
  • RWTH Aachen University
  • University of South Carolina