A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Feb 20, 2022
- Source ID
- 10.1109/isscc42614.2022.9731582
Entities
People
- Dejan Marković
- Subramanian Iyer
- Sumeet Singh Nagi
- Uneeb Rathore
Organizations
- University of California, Los Angeles