A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI

Document Details

Document Type
Pub Defense Publication
Publication Date
Jul 01, 2017
Source ID
10.1109/jssc.2017.2690859

Entities

People

  • Alberto Puggelli
  • Ben Keller
  • Borivoje Nikolic
  • Brian Zimmer
  • Colin Schmidt
  • Elad Alon
  • Jaehwa Kwak
  • Krste Asanovic
  • Martin Cochet
  • Milovan Blagojevic
  • Palmer Dabbelt
  • Pi-Feng Chiu
  • Stevo Bailey
  • Yunsup Lee

Organizations

  • AMD
  • Division of Graduate Education
  • Intel Corporation
  • National Science Foundation
  • Nvidia