Reprogrammable Redundancy for SRAM-Based Cache $V_{\min }$ Reduction in a 28-nm RISC-V Processor

Document Details

Document Type
Pub Defense Publication
Publication Date
Oct 01, 2017
Source ID
10.1109/jssc.2017.2715798

Entities

People

  • Borivoje Nikolic
  • Brian Zimmer
  • Krste Asanovic
  • Pi-Feng Chiu

Organizations

  • TSMC