Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory

Document Details

Document Type
Pub Defense Publication
Publication Date
Apr 01, 2022
Source ID
10.1109/jssc.2022.3140241

Entities

People

  • Alhad Daftardar
  • Chaitali Chakrabarti
  • David Blaauw
  • Hun-Seok Kim
  • Jielun Tan
  • Kuan-Yu Chen
  • Morteza Fayazi
  • Ronald Dreslinski
  • Subhankar Pal
  • Sung Kim
  • Trevor Mudge
  • Tutu Ajayi
  • Yan Xiong

Organizations

  • Arizona State University
  • Defense Advanced Research Projects Agency
  • Federal Government of the United States
  • Qualcomm
  • University of Michigan