A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration

Document Details

Document Type
Pub Defense Publication
Publication Date
Jan 01, 2023
Source ID
10.1109/jssc.2022.3212685

Entities

People

  • Dejan Marković
  • Krutikesh Sahoo
  • Subramanian S. Iyer
  • Sumeet Singh Nagi
  • Tim Ling
  • Uneeb Rathore

Organizations

  • Defense Advanced Research Projects Agency
  • University of California, Los Angeles