CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 2023
- Source ID
- 10.1109/lssc.2023.3303111
Entities
People
- Ang Li
- August Ning
- Christopher Batten
- David Wentzlaff
- Eric Tang
- Fei Gao
- Georgios Tziantzioulis
- Grigory Chirkov
- Jinzheng Tu
- Jonathan Balkind
- Kaifeng Xu
- Marcelo Orenes-vera
- Moyang Wang
- P.J. Jackson
- Shady Agwa
- Ting-jung Chang
- Tuan Ta
- Xiaoyu Yan
- Yanghui Ou
Organizations
- Air Force Research Laboratory
- Cornell University
- Defense Advanced Research Projects Agency
- Princeton University
- University of California, Santa Barbara