Hill-climbing SMT processor resource distribution
Abstract
The key to high performance in Simultaneous MultiThreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distribution techniques optimize performance only indirectly. They infer potential performance bottlenecks by observing indicators, like instruction occupancy or cache miss counts, and take actions to try to alleviate them. While the corrective actions are designed to improve performance, their actual performance impact is not known since end performance is never monitored. Consequently, potential performance gains are lost whenever the corrective actions do not effectively address the actual bottlenecks occurring in the pipeline.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Feb 01, 2009
- Source ID
- 10.1145/1482619.1482620
Entities
People
- Donald Yeung
- Seungryul Choi
Organizations
- Air Force Research Laboratory
- Defense Advanced Research Projects Agency
- National Science Foundation
- University of Maryland