Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
Abstract
In this article we demonstrate a floating point FFT processor that leverages both 3D integration and a unique hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227 μJ . The hypercube memory division scheme lowers the energy per memory access by 59.2% and increases the total required area by 16.8%. The use of 3D integration reduces the logic power by 5.2%. We describe the tool flow required to realize the 3D implementation and perform a thermal analysis of it.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Nov 01, 2010
- Source ID
- 10.1145/1870109.1870114
Entities
People
- Paul D Franzon
- Samson Melamed
- Thorlindur Thorolfsson
- W. Rhett Davis
Organizations
- Defense Advanced Research Projects Agency
- North Carolina State University