Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors
Abstract
Integrated photonics has been slated as a revolutionary technology with the potential to mitigate the many challenges associated with on- and off-chip electrical interconnection networks. To date, all proposed chip-scale photonic interconnects have been based on the crystalline silicon platform for CMOS-compatible fabrication. However, maintaining CMOS compatibility does not preclude the use of other CMOS-compatible silicon materials such as silicon nitride and polycrystalline silicon. In this work, we investigate utilizing devices based on these deposited materials to design photonic networks with multiple layers of photonic devices. We apply rigorous device optimization and insertion loss analysis on various network architectures, demonstrating that multilayer photonic networks can exhibit dramatically lower total insertion loss, enabling unprecedented bandwidth scalability. We show that significant improvements in waveguide propagation and waveguide crossing insertion losses resulting from using these materials enables the realization of topologies that were previously not feasible using only the single-layer crystalline silicon approaches.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jun 01, 2011
- Source ID
- 10.1145/1970406.1970409
Entities
People
- Aleksandr Biberman
- Gilbert Hendry
- Jacob S. Levy
- Johnnie Chan
- Keren Bergman
- Kyle Preston
- Michal Lipson
- Nicolás Sherwood-droz
Organizations
- Air Force Office of Scientific Research
- Columbia University
- Cornell University
- Division of Electrical, Communications & Cyber Systems
- National Science Foundation
- Semiconductor Research Corporation