A transactional memory with automatic performance tuning
Abstract
A significant obstacle to the acceptance of transactional memory (TM) in real-world parallel programs is the abundance of substantially different TM algorithms. Each TM algorithm appears well-suited to certain workload characteristics, but the best choice of algorithm is sensitive to program inputs, available cores, and program phases. Furthermore, operating system and hardware characteristics can affect which algorithm is best, with tradeoffs changing across iterations of a single ISA.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 2012
- Source ID
- 10.1145/2086696.2086733
Entities
People
- John Cavazos
- Michael Spear
- Qingping Wang
- Sameer G. Kulkarni
Organizations
- Defense Advanced Research Projects Agency
- Division of Computer and Network Systems
- Lehigh University
- National Science Foundation
- University of Delaware