ZSim
Abstract
Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jun 23, 2013
- Source ID
- 10.1145/2508148.2485963
Entities
People
- Christos Kozyrakis
- Daniel Sanchez
Organizations
- Defense Advanced Research Projects Agency
- Massachusetts Institute of Technology
- Stanford University