Centip3De
Abstract
Process scaling has resulted in an exponential increase of the number of transistors available to designers. Meanwhile, global interconnect has not scaled nearly as well, because global wires scale only in one dimension instead of two, resulting in fewer, high-resistance routing tracks. This paper evaluates the use of three-dimensional (3D) integration to reduce global interconnect by adding multiple layers of silicon with vertical connections between them using through-silicon vias (TSVs). Because global interconnect can be millimeters long, and silicon layers tend to be only tens of microns thick in 3D stacked processes, the power and performance gains by using vertical interconnect can be substantial. To address the thermal issues that arise with 3D integration, this paper also evaluates the use of near-threshold computing---operating the system at a supply voltage just above the threshold voltage of the transistors.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Nov 01, 2013
- Source ID
- 10.1145/2524713.2524725
Entities
People
- Bharan Giridhar
- Daeyeon Kim
- David Blaauw
- David Fick
- Dennis Sylvester
- Gregory Chen
- Gyouho Kim
- Matthew Fojtik
- Michael Wieckowski
- Nurrachman Liu
- Ronald G. Dreslinski
- Sangwon Seo
- Sudhir Satpathy
- Trevor Mudge
- Yoonmyung Lee
Organizations
- Arm Holdings
- Defense Advanced Research Projects Agency
- National Science Foundation
- University of Michigan