Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip
Abstract
Traditional metal-wire-based networks-on-chip (NoC) suffer from high latency and power dissipation as the system size scales up in the number of cores. This limitation stems from the inherent multihop communication nature of larger NoCs. It has previously been shown that the performance of NoCs can be significantly improved by introducing long-range, low power, and high-bandwidth single-hop links between distant cores. While previous work has focused on specific NoC architectures and configurations, it remains an open question whether heterogeneous link types are beneficial in a broad range of NoC architectures. In this article, we show that a generic NoC architecture with heterogeneous link types allows for NoCs with higher bandwidth at a lower cost compared to homogeneous networks. We further show that such NoCs scale up significantly better in terms of performance and cost. We demonstrate these broadly-applicable results by using a technology-agnostic complex network approach that targets NoC architectures with various emerging link types.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Apr 01, 2014
- Source ID
- 10.1145/2567666
Entities
People
- Christof Teuscher
- Haera Chung
- Partha Pande
Organizations
- Defense Advanced Research Projects Agency
- Portland State University
- Washington State University