Darkroom
Abstract
Specialized image signal processors (ISPs) exploit the structure of image processing pipelines to minimize memory bandwidth using the architectural pattern of line-buffering , where all intermediate data between each stage is stored in small on-chip buffers. This provides high energy efficiency, allowing long pipelines with tera-op/sec. image processing in battery-powered devices, but traditionally requires painstaking manual design in hardware. Based on this pattern, we present Darkroom, a language and compiler for image processing. The semantics of the Darkroom language allow it to compile programs directly into line-buffered pipelines, with all intermediate values in local line-buffer storage, eliminating unnecessary communication with off-chip DRAM. We formulate the problem of optimally scheduling line-buffered pipelines to minimize buffering as an integer linear program. Finally, given an optimally scheduled pipeline, Darkroom synthesizes hardware descriptions for ASIC or FPGA, or fast CPU code. We evaluate Darkroom implementations of a range of applications, including a camera pipeline, low-level feature detection algorithms, and deblurring. For many applications, we demonstrate gigapixel/sec. performance in under 0.5mm 2 of ASIC silicon at 250 mW (simulated on a 45nm foundry process), real-time 1080p/60 video processing using a fraction of the resources of a modern FPGA, and tens of megapixels/sec. of throughput on a quad-core x86 processor.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jul 27, 2014
- Source ID
- 10.1145/2601097.2601174
Entities
People
- Artem Vasilyev
- James Hegarty
- John Brunhaver
- Jonathan Ragan-Kelley
- Mark Horowitz
- Noy Cohen
- Pat Hanrahan
- Steven Bell
- Zachary Devito
Organizations
- Defense Advanced Research Projects Agency
- Intel Corporation
- Massachusetts Institute of Technology
- Nvidia
- Office of Advanced Scientific Computing Research
- Stanford University