Compiler-assisted detection of transient memory errors
Abstract
The probability of bit flips in hardware memory systems is projected to increase significantly as memory systems continue to scale in size and complexity. Effective hardware-based error detection and correction require that the complete data path, involving all parts of the memory system, be protected with sufficient redundancy. First, this may be costly to employ on commodity computing platforms, and second, even on high-end systems, protection against multi-bit errors may be lacking. Therefore, augmenting hardware error detection schemes with software techniques is of considerable interest.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jun 05, 2014
- Source ID
- 10.1145/2666356.2594298
Entities
People
- P. Sadayappan
- Sanket Tavarageri
- Sriram Krishnamoorthy
Organizations
- Ohio State University
- Pacific Northwest National Laboratory
- United States Department of Defense
- United States Department of Energy