Aladdin
Abstract
Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jun 14, 2014
- Source ID
- 10.1145/2678373.2665689
Entities
People
- Brandon Reagen
- David Brooks
- Gu-yeon Wei
- Yakun Sophia Shao
Organizations
- Defense Advanced Research Projects Agency
- Division of Computing and Communication Foundations
- Harvard University