Architecture implications of pads as a scarce resource
Abstract
Due to non-ideal technology scaling, delivering a stable supply voltage is increasingly challenging. Furthermore, com- petition for limited chip interface resources (i.e., C4 pads) between power supply and I/O, and the loss of such resources to electromigration, means that constructing a power deliverynetwork (PDN) that satisfies noise margins without compromising performance is and will remain a critical problem for architects and circuit designers alike. Simple guardbanding will no longer work, as the consequent performance penalty will grow with technology scaling
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jun 14, 2014
- Source ID
- 10.1145/2678373.2665728
Entities
People
- Brett H. Meyer
- Ke Wang
- Kevin Skadron
- Mircea R. Stan
- Runjie Zhang
Organizations
- Defense Advanced Research Projects Agency
- Division of Computer and Network Systems
- National Science Foundation
- University of Virginia