Improving the energy efficiency of big cores
Abstract
Traditionally, architectural innovations designed to boost single-threaded performance incur overhead costs which significantly increase power consumption. In many cases the increase in power exceeds the improvement in performance, resulting in a net increase in energy consumption. Thus, it is reasonable to assume that modern attempts to improve singlethreaded performance will have a negative impact on energy efficiency. This has led to the belief that "Big Cores" are inherently inefficient. To the contrary, we present a study which finds that the increased complexity of the core microarchitecture in recent generations of the IntelR Core™ processor have reduced both the time and energy required to run various workloads. Moreover, taking out the impact of process technology changes, our study still finds the architecture and microarchitecture changes ---such as the increase in SIMD width, addition of the frontend caches, and the enhancement to the out-of-order execution engine--- account for 1.2x improvement in energy efficiency for these processors. This paper provides real-world examples of how architectural innovations can mitigate inefficiencies associated with "Big Cores" ---for example, micro-op caches obviate the costly decode of complex x86 instructions--- resulting in a core architecture that is both high performance and energy efficient. It also contributes to the understanding of how microarchitecture affects performance, power and energy efficiency by modeling the relationship between them
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jun 14, 2014
- Source ID
- 10.1145/2678373.2665743
Entities
People
- Ed Grochowski
- Kenneth Czechowski
- Pradeep Dubey
- Richard Vuduc
- Ronak Singhal
- Ronny Ronen
- Victor W. Lee
Organizations
- Defense Advanced Research Projects Agency
- Georgia Tech
- Intel Corporation
- National Science Foundation