Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance Analysis
Abstract
To enable performance improvements in a power-efficient manner, computer architects have been building CPUs that exploit greater amounts of thread-level parallelism. A key consideration in such CPUs is properly designing the on-chip cache hierarchy. Unfortunately, this can be hard to do, especially for CPUs with high core counts and large amounts of cache. The enormous design space formed by the combinatorial number of ways in which to organize the cache hierarchy makes it difficult to identify power-efficient configurations. Moreover, the problem is exacerbated by the slow speed of architectural simulation, which is the primary means for conducting such design space studies.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Apr 06, 2016
- Source ID
- 10.1145/2851503
Entities
People
- Donald Yeung
- Jeff Casarona
- Michael Badamo
- Minshu Zhao
Organizations
- Defense Advanced Research Projects Agency
- National Science Foundation
- University of Maryland