Generating Configurable Hardware from Parallel Patterns
Abstract
In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and energy improvements over CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two important optimizations for using parallel patterns to generate efficient hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 39.4× on a set of benchmarks from the data analytics domain.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Mar 25, 2016
- Source ID
- 10.1145/2954679.2872415
Entities
People
- Christopher De Sa
- Christos Kozyrakis
- David Koeplinger
- Hyoukjoong Lee
- Kevin J. Brown
- Kunle Olukotun
- Raghu Prabhakar
Organizations
- Defense Advanced Research Projects Agency
- National Science Foundation
- Stanford University
- United States Department of Energy