High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics
Abstract
With its applicability spanning numerous data-driven fields, the implementation of graph analytics on multicore platforms is gaining momentum. One of the most important components of a multicore chip is its communication backbone. Due to inherent irregularities in data movements manifested by graph-based applications, it is essential to design efficient on-chip interconnection architectures for multicore chips performing graph analytics. In this article, we present a detailed analysis of the traffic patterns generated by graph-based applications when mapped to multicore chips. Based on this analysis, we explore the design-space for the Network-on-Chip (NoC) architecture to enable an efficient implementation of graph analytics. We principally consider three types of NoC architectures, viz., traditional mesh, small-world, and high-radix networks. We demonstrate that the small-world-network-enabled wireless NoC (WiNoC) is the most suitable platform for executing the considered graph applications. The WiNoC achieves an average of 38% and 18% full-system Energy Delay Product savings compared to wireline-mesh and high-radix NoCs, respectively.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Sep 01, 2016
- Source ID
- 10.1145/2961027
Entities
People
- Ananth Kalyanaraman
- H. Lu
- Karthi Duraisamy
- Partha Pratim Pande
Organizations
- Army Research Office
- National Science Foundation
- United States Department of Energy
- Washington State University