Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration
Abstract
The Von Neumann architecture, defined by strict and hierarchical separation of memory and processor, has been a hallmark of conventional computer design since the 1940s. It is becoming increasingly unsuitable for cognitive applications, which require massive parallel processing of highly interdependent data. Inspired by the brain, we propose a significantly different architecture characterized by a large number of highly interconnected simple processors intertwined with very large amounts of low-latency memory. We contend that this memory-centric architecture can be realized using 3D wafer scale integration for which the technology is nearing readiness, combined with current CMOS device technologies. The natural fault tolerance and lower power requirements of neuromorphic processing make 3D wafer stacking particularly attractive. In order to assess the performance of this architecture, we propose a specific embodiment of a neuronal system using 3D wafer scale integration; formulate a simple model of brain connectivity including short- and long-range connections; and estimate the memory, bandwidth, latency, and power requirements of the system using the connectivity model. We find that 3D wafer scale integration, combined with technologies nearing readiness, offers the potential for scaleup to a primate-scale brain, while further scaleup to a human-scale brain would require significant additional innovations.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Apr 20, 2017
- Source ID
- 10.1145/2976742
Entities
People
- Arvind Kumar
- Subramanian Iyer
- Winfried W. Wilcke
- Zhe Wan
Organizations
- Defense Advanced Research Projects Agency
- International Business Machines Corporation (Armonk, NY)
- University of California, Los Angeles