A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process
Abstract
We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Nov 03, 2021
- Source ID
- 10.1145/3466681
Entities
People
- Daehyun Kim
- Edward A. Lee
- Jinwoo Kim
- Saibal Mukhopadhyay
- Sung Kyu Lim
Organizations
- Defense Advanced Research Projects Agency
- Georgia Tech