Analysis and Design of Regular Structures for Robust Dynamic Fault Testability
Abstract
Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay, transistor stuck-open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum-of-products form, minimizing the cover to obtain a fully dynamic-fault testable two-level representation of the functions, and performing structural transformations to resynthesize the circuit into a multilevel network, while also maintaining full dynamic-fault testability. While this technique will work well for random or control logic, it is not practical for many regular structures.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 1993
- Source ID
- 10.1155/1993/38536
Entities
People
- Kurt Keutzer
- Michael J. Bryan
- Srinivas Devadas
Organizations
- Defense Advanced Research Projects Agency
- Massachusetts Institute of Technology
- Synopsys