Hierarchical Process Simulation for Nano-Electronics
Abstract
The challenges of computational electronics are considered from the perspective of process simulation. Essential limitations for device scaling posed from a technology point of view are discussed along with many new research opportunities. The key areas considered include: bulk processing, interconnect technology and software engineering for computational electronics.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 1998
- Source ID
- 10.1155/1998/19402
Entities
People
- Edwin C Kan
- Robert W. Dutton
Organizations
- Cornell University
- Defense Advanced Research Projects Agency
- Stanford University