Power Distribution Synthesis for VLSI
Abstract
The synthesis of the power distribution network is an important problem in the layout design of VLSI systems. In this paper we propose novel methods to solve the problem of designing minimal area power distribution nets, while satisfying voltage drop and electromigration constraints. We will see that our methods significantly improve upon current techniques. We propose two novel greedy heuristics for power net design-one based on bottom-up tree construction using greedy merging and the other based on top-down linearly separable partitioning. We test the efficacy of our techniques on benchmark instances. The areas required by our methods on typical instances are significantly smaller than those obtained using previous methods.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 1998
- Source ID
- 10.1155/1998/76525
Entities
People
- Ashok Vittal
- Malgorzata Marek-sadowska
Organizations
- Defense Advanced Research Projects Agency
- University of California