Architectural Power Estimation Based on Behavior Level Profiling
Abstract
High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 1998
- Source ID
- 10.1155/1998/93106
Entities
People
- Ranga Vemuri
- Srinivas Katkoori
Organizations
- United States Air Force
- University of Cincinnati
- University of South Florida