Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability
Abstract
Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 μm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 2001
- Source ID
- 10.1155/2001/90787
Entities
People
- Amr Haggag
- Björn Fischer
- Karl Hess
- Leonard F. Register
- William Mcmahon
Organizations
- Office of Naval Research
- University of Illinois Urbana–Champaign
- University of Texas at Austin