Multi-FPGA Partitioning Method Based on Topological Levelization
Abstract
This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms.
Document Details
- Document Type
- Pub Defense Publication
- Publication Date
- Jan 01, 2010
- Source ID
- 10.1155/2010/709487
Entities
People
- Amr Elchouemi
- Don Bouldin
- Nabil Kerkiz
Organizations
- Defense Advanced Research Projects Agency
- University of Tennessee