Common Heterogeneous integration & IP reuse Strategies (CHIPS)*
Abstract
*Formerly Fast and Big Mixed-Signal Designs (FAB) The scaling of silicon transistors to ever smaller dimensions has led to dramatic gains in processor performance over the past forty years. In parallel, IC designers for RF circuits have leveraged the different material properties of compound semiconductor (CS) technologies such as gallium arsenide (GaAs), gallium nitride (GaN) and silicon-germanium (SiGe) to enable devices that operate at frequencies and powers difficult or impossible to achieve in silicon. When integrated together the heterogeneous integration of these technologies has been demonstrated to far exceed what can be accomplished with any one technology alone. The process of integrating CS technologies on silicon currently requires that the silicon transistor dimension, or process node, be fixed which requires designs to be remade for various combinations of technology and process node, a costly and time consuming effort. This program will investigate the potential for a truly process-agnostic integration technology that is inclusive of any current or future circuit fabrication technology with a standardized interconnect topology. Such a technology platform will enable the design of individual circuit intellectual property (IP) blocks, such as low-noise amplifiers or analog-to-digital converters (ADC), with a goal of re-using them across applications and resulting in time and cost savings. Re-use will allow the DoD to spread the upfront design cost of these blocks over several designs instead of leveling the burden on a single program. Furthermore, the IP can be designed in the fabrication process best suited for the performance goals and evolve more quickly than larger, more expensive single-chip (monolithic) systems-on-a-chip. Through standardization of the interface, CHIPS will enable the DoD to leverage the advancements driven by the global semiconductor market rather than relying on a single on-shore foundry provider or on proprietary circuit designs owned by a few traditional prime performers. In the Applied Research part of this program, focus will be placed on the rapid development and insertion of microsystems utilizing the CHIPS technology. For example, the development of an ADC combining a SiGe circuit integrated with 14 nanometer Silicon CMOS will be explored. This program has advanced technology development efforts funded in PE 0603739E, Project MT-15.
Document Details
- Document Type
- Accomplishment
- Publication Date
- Oct 01, 2017
- Source ID
- 3f8cb98407cf5205e9f917d0634c37b2
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- Root: ELECTRONICS TECHNOLOGY