Verification & Validation (V&V) Capabilities and Standards for Trust

Abstract

This project improves microelectronics test and verification methodologies in support of verifying the trust and assurance of parts and develops standards and practices to foster commercial development of secure, trusted and assured parts. Verification and test technologies are required to provide direct program support for microelectronics assurance verification when DoD Trusted Foundry Program options are not available. Core technical laboratories and other HwA and SwA capabilities are chartered as a JFAC to provide this support. Out-year demands will require an increase in capacity, which will take the form of additional personnel and/or equipment to permit scaling of microelectronics assessment capabilities. Challenges have been identified, to include the ability to analyze leading-edge technology nodes (<45 nanometers (nm)), throughput/time required for analysis, ability to analyze third-party IP contained in microelectronic components, and analysis of non-application specific integrated circuit (ASIC) components that are increasingly being used for agility, e.g., Field-Programmable Gate Arrays (FPGAs). This project addresses these gaps in current technical capabilities, in coordination with the JFAC, which prioritizes this investment as required to meet the realized and projected out-year demand for JFAC services. Three capability areas core to microelectronics analysis and verification will be improved: • Physical verification, i.e., destructive analysis of integrated circuits and printed circuit boards. • Functional analysis, i.e., non-destructive screening/verification of select, critical parts. • Design verification, i.e., verification/assurance of designs, IP, netlists, bitstreams, firmware, etc. These improvements address two primary attributes: (1) technical capability including laboratory equipment, IP, analysis tools, such as imaging software, and highly skilled tradecraft, and (2) the capacity to perform microelectronics assessments. This project develops and matures assurance mitigations, evaluates the effectiveness of protections of IP in support of integrity, and develops and validates obfuscation and disaggregation technologies. The project will address physical validation tool and capability development, design software validation tool development, counterfeit detection and imaging techniques, and system vulnerability assessments and testbeds. This project also develops standards and practices in support of assured designs and supply chains and formal relationships with industry to foster commercial development of secure, trusted, and assured parts and for acquisition of USG access to proprietary designs, software, development, and quality assurance processes and test procedures to develop practices that minimize security flaws in designs and facilitate verification. Two capability areas that are core to improved commercial designs will be improved, i.e., assured designs and supply chains.

Document Details

• Document Type: Project
• Publication Date: Oct 01, 2020
• Source ID: 645_0604294D8Z_4_0400_PB_2020

Tags

Fields of Study

• Computer science

Readers

• Cybersecurity.
• Integrated Circuit Design and Technology.
• Military Science and Technology Research and Modernization.

Technology Areas

• Microelectronics