Digital Bit Synchronizer.
Abstract
The patent application describes a system for deriving synchronizing pulses from a train of digital signals that is fed to in-phase and mid-phase gates each including an adder with a delay feedback. The output of the mid-phase gate is multiplied by a sign factor determined by a logic circuit connected to the in-phase gate. The output of the two gates are then mixed, filtered, and summed with a value dependent upon the clock rate and fed to a number controlled oscillator which includes a counter and a comparing circuit. The output of the number controlled oscillator is fed back to the in-phase and mid-phase gates.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 14, 1972
- Accession Number
- AD0164614
Entities
People
- Francis D. Natali
Organizations
- United States Department of the Air Force