HIGH EFFICIENCY TRANSISTOR STRUCTURES

Abstract

Efforts are concerned with providing the military with reliable switching transistors which operate at such low power levels that they reduce the over-all power consumption of computer systems by at least one order of magnitude and allow a much higher packing density of components because of the reduced power dissipation. High efficiency of transistor circuitry at very low power levels is one of the crucial prerequisites for successful systems miniaturization. Based on the knowledge of the behavior of pn-junctions at low current densities and voltages the dc parameters of the transistor and their dependence on geometry, doping and crystal imperfection were derived. The switching speed of the transistor at low power levels is discussed. By controlling the crystal imperfections and pushing the dimensions of the transistor to the utmost limit, switching times of lower than 10 to the -6th power sec at micron watt level are feasible in specially designed switching circuits. (Author)

Document Details

Document Type
Technical Report
Publication Date
Apr 20, 1961
Accession Number
AD0261522

Entities

People

  • M. Schuller

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuits
  • Computers
  • Current Density
  • Dissipation
  • Efficiency
  • Energy Consumption
  • Geometry
  • Miniaturization
  • P-N Junctions
  • Packing Density
  • Power Levels
  • Switching
  • Switching Circuits
  • Transistors

Readers

  • Electrical Engineering
  • Integrated Circuit Design and Technology.
  • Materials Science and Engineering.