LINEAR RECURRENT BINARY ERROR-BURST-CODER
Abstract
The construction and testing of a binary error burst-correcting channel simulator and decoder are described. The equipment was constructed from standard binary logic units. The channel simulator (encoder) is not general owing to the linearity of the code and the chosen message sequence of all zeros. It can generate random errors and parity check digits, open the channel gate during a burst and close it during a guard space, and preserve all phase relations. The decoder can compare information digits with parity digits, establish a correction sequence and locate its largest axis, and correct the digits which are in error. The testing procedure uses 2 electronic counters in conjunction with encoder-decoder. One is used to count errors entering the decoder; the other to count those leaving the decoder. Thus, the error correcting efficiency is easily calculated. Test results show perfect correction with a guard space of 132 digits. With guard lengths below 132, better correction efficiency is achieved if the probability of an error during a burst is high. An analytical interpretation of test data is given.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 23, 1961
- Accession Number
- AD0273741
Entities
People
- Charles Skyes
- Daniel N. March
- Richard W. Weeks
- William L. Kilmer