INTERDIGITATED SILICON TRANSISTOR PROGRAM
Abstract
The 10, 50, and 100 ampere device designs were completed. Some 10 and 20 ampere planar transistors were fabricated, and indications are that by the elimination of all thermal oxidations of the collector surface, the collector-base reverse leakage can be reduced. An electrochemical polishing technique was tried that showed promise. A decision was made to employ a horizontal RF-heated reactor for epitaxial collector deposition, and construction is under way. Some progress was made in the development of a vapor technique for predepositing the base dopant on the wafer. Three package sizes will be required to house all five types of transistors, each utilizing ceramic insulators. Packages will be sealed by cold welding. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 29, 1962
- Accession Number
- AD0277515
Entities
People
- B. Rappaport
- F.j. Steinebrey