FAILURE TOLERANCE IMPROVEMENT IN PARALLEL CORE MEMORIES BY MEANS OF WORD SPLIT TECHNIQUE

Abstract

A method is presented for improving the failure tolerance level in parallel random access core memories. It is shown that degraded operational modes can be organized with almost no additional hardware in the memory and that the probability of 100 percent memory failure can be significantly reduced. The gain in cost or reliability depends on several parameters, such as partitioning in the original organization, redundancy factor, contents of the memory (data or instructions) and memory allocation. (Author)

Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1962
Accession Number
AD0292677

Entities

People

  • A. Holick

Tags

DTIC Thesaurus Topics

  • Instructions
  • Probability
  • Redundancy

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computer Engineering
  • Operations Research