ANTICIPATED CARRY-MAJORITY LOGIC MODE
Abstract
The use of the majority (2 out of 3) logic element in anticipated carries for adders, multipliers, etc., yields very fast designs with only a moderate number of gates. The general theory of such carries is presented. This is applied to the design of a 48-bit adder. One hundred and sixty-four majority gates give carries for all 48 bits with a maximum of 6 stages of delay. The relationship between delay and quality of gates required is plotted.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 1963
- Accession Number
- AD0407560
Entities
People
- R. A. Knoebel
Organizations
- MITRE Corporation