TECHNOLOGY FOR PNP PLANAR SILICON TRANSISTORS: SWITCHING AND AMPLIFYING
Abstract
Processes and techniques required for fabrication of experimental planar PNP silicon transistors were developed and demonstrated as feasible. Processes involved include material preparation, antimony base diffusion, boron emitter diffusion, oxide masking, photoresist techniques, simultaneous gold metalizing of emitter and base regions, collector alloy contact and basing, and thermocompression bonding. Initial transistors have typical dc Beta values of 35 to 40 and FT values as high as 350 MCS. Processes described were also used in preliminary fabrication of solid state microcircuit passive components.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1963
- Accession Number
- AD0408190
Entities
People
- Alex Rogel
- Armond P. Larocque
- Raymond Jackson
- Robert S. Yatsko
- Vincent E. Rible
Organizations
- United States Army Communications-Electronics Command