Development of PNP High Speed Switching Transistor
Abstract
Development of the PNP high-speed silicon switching transistor is discussed in detail with emphasis on the design parameters. Problems associated with each of the design parameters are stated and discussed. The methods of approach along with the experimental results are presented for each problem area and the over-all conclusions based upon these experimental results summarize the technical effort of the program. Recommendations are also presented for possible improvement of the transistor. The diffusion and contact procedures as well as the material and electrical specifications are presented in detail enabling a competent technician to produce the developed switching transistor. Specifically, the transistor has a typical total switching time of 35 nanoseconds and a typical cutoff frequency of 800 megacycles. The delay and rise times are 3.3 and 4.0 nsec respectively. The storage time is 15 nsec. The fall time averages 12 nsec. Gold diffusion would have reduced the storage, but would have had other undesirable effects.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 30, 1964
- Accession Number
- AD0443686
Entities
People
- John Blair
- Larry G. Lands
- Paul C. Nagle
- Robert P. Williams
Organizations
- Texas Instruments