RESEARCH AND DEVELOPMENT INVESTIGATION OF A PRECISION DIGITAL FREQUENCY SYNTHESIZER FOR SSB.
Abstract
This is the second quarterly report of a 1-year research and development investigation of a low power frequency synthesizer for ssb application. The first quarterly report presented a design plan that was believed to offer the optimum in meeting all the performance goals. Also presented were alternate methods that offered advantages in some areas at the cost of performance in other areas. The principal design plan placed primary weight on power dissipation. The cost was circuit complexity and a degradation of miniature packaging capability. This report has taken the principal design plan and the most promising alternate and made a comparison of the circuit parameters, performance, power dissipation, circuitry, and potential packaging. This report also presents design nomographs, which show the relationship between the phase lock feedback loop parameters and characteristics. The report has included power dissipation estimates for the two design plans being considered. Power estimates are also made for available voltages of 12 volts only, 12 volts and 3 volts, or 3 volts only. Experimental results are reported on low-power, low speed, digital circuits; and on low-power, high-speed digital circuits. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 12, 1965
- Accession Number
- AD0462497
Entities
People
- T. C. Thomas