DETAILED STUDY OF DELETERIOUS EFFECTS ON SILICON TRANSISTORS.
Abstract
A summary on common emitter DC gain degradation phenomena on NPN transistors is given. The hFE degradation, with respect to non-bias temperature stress, reverse bias plus temperature stress, operating life stress, encapsulating ambient, surface contamination, surface coating, etc., is discussed. Also models for hFE degradation are presented. The reasons why the surface sensitive parameters are not closely correlated are discussed. Silicon p-n junction leakage current phenomena are analyzed utilizing observations made on nonoverlay oxide passivated PNP transistors, overlay high-frequency interdigitated PNP transistors, MOS field effect transistors and experiments conducted with special geometry n- or p-type diodes. A model for p-n junction leakage current which explains three types of currents, (1) bulk depletion layer generation current, (2) surface channel generation current and (3) direct channel conduction current, is presented. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1965
- Accession Number
- AD0465920
Entities
People
- Ki Dong Kang
Organizations
- Motorola Mobility